Systematic and automatic testing of integrated circuits becomes increasingly important. With each new generation of integrated circuits component density, number of system functionalities, and clock speed are substantially increased. Integrated circuits have reached such complexity and speed that process defects are no longer detectable using even the most exhaustive and expensive conventional testing procedures. However, customers will not accept products that show their hidden defects in operational use, thereby rendering, for example, life support systems or aircraft control systems unreliable.
At the present time, embedded semiconductor memories are operating at high speed with clock cycles reaching 2 ns for SRAMS, or even less for the new generation of CMOS whose critical dimensions are on the order of 90 nanometers. Testing of the embedded semiconductor memories is generally performed by Built-In-Self-Test (BIST) or a tester using scan test mode. In the BIST—or the tester—consecutive test patterns are generated to perform read and write operations at the memory, according to a predetermined March test. The march test is well known in the art and is often considered a sufficient test for semiconductor memories.
Resistive open defects not only cause static faulty behavior of the semiconductor memory, which is easily detected, but also dynamic faulty behavior known as “slow to rise” and “slow to fall” either in the data path or the address path. Depending on the resistance of the defect—defect size—the delays vary considerably. Big delays resulting in static faulty behavior are easily detected. The detection of small delays corresponding to small sized defects requires high speed testing using the BIST or scan test. Ideally, the semiconductor memories need to be tested at their operating frequency. If a semiconductor memory is not tested at the operating frequency, small sized resistive open defects are not detected even with the correct test patterns applied. However, a high speed BIST is not easily incorporated into the memory layout, because of the delay needed for the output analyzer of the BIST, the extra time needed for the synthesis, and the additional area needed for the high speed BIST. Increasing the speed of the BIST implies a substantial increase in area for the BIST, which is unacceptable for most applications. Furthermore, testing embedded semiconductor memories using scan test mode needs additional test time due to scan-in and scan-out of the data, which is done in series, and, therefore, substantially increases the test time for big memories with a high number of pins.
As modern fabrication process change from aluminum-based interconnect to a copper-based interconnect, resistive-open defects are becoming the dominant defects. For example, in an aluminum process, resistive metal bridging is more prevalent than resistive opens. In contracts, in a copper process, resistive opens are more prevalent.
However, as outlined above, testing at frequencies below the operating frequency of a semiconductor memory may result in undetected delay faults such as those manifested by resistive open defects, resistive bridges, and capacitive coupling.
There is a need to provide a method for reliably detecting delay faults in new generation semiconductor memories using a BIST or tester operating at a lower frequency than the operating frequency of the semiconductor memory.